View HI-1573_730379.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HI-1573, HI-1574
May 2003
MIL-STD-1553 3.3V Monolithic Dual Transceivers
PIN CONFIGURATIONS
44 43 BUSA 42 BUSA 41 BUSA 40 BUSA 39 VDDA 38 VDDA 37 TXA 36 TXA 35 34 -1 RXENA 2 GNDA 3 GNDA 4 GNDA 5 VDDB 6 VDDB 7 BUSB 8 BUSB 9 BUSB 10 BUSB 11
DESCRIPTION
The HI-1573 and HI-1574 are low power CMOS dual transceivers designed to meet the requirements of the MIL-STD-1553 specification. The transmitter section of each channel takes complementary CMOS / TTL digital input data and converts it to bi-phase Manchester encoded 1553 signals suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. The receiver section of the each channel converts the 1553 bus bi-phase data to complementary CMOS / TTL data suitable for inputting to a Manchester decoder. Each receiver has a separate enable input which can be used to force the output of the receiver to a logic "0" (HI-1573) or logic 1 (HI-1574). To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. For designs requiring independent access to transmitter and receiver 1553 signals, please contact your Holt Sales representative.
1573PCI 1573PCT 1574PCI 1574PCT
33 32 31 TXINHA 30 RXA 29 RXA 28 27 26 TXB 25 TXB 24 TXINHB 23 -
44 Pin Plastic 7mm x 7mm Chip-scale package
VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 20 19 18 17 16 15 14 13 12 11 TXA TXA TXINHA RXA RXA TXB TXB TXINHB RXB RXB
FEATURES
! Compliant to MIL-STD-1553A & B,
ARINC 708A
! 3.3V single supply operation ! Smallest footprint available in 44-pin plastic
7 mm x 7 mm chip-scale package with integral heatsink
20 Pin Plastic ESOIC - WB package
VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 20 TXA 19 TXA
! Less than 0.5W maximum power dissipation ! Also available in DIP and small outline
(ESOIC) package options
! Military processing options ! Industry standard pin configurations
(DS1573 Rev.D)
20 Pin Ceramic DIP package
05/03
HOLT INTEGRATED CIRCUITS www.holtic.com
RXENB GNDB GNDB GNDB RXB RXB -
12 13 14 15 16 17 18 19 20 21 22
1573PSI 1573PST 1573PSM 1574PSI 1574PST 1574PSM
1573CDI 1573CDT 1573CDM 1574CDI 1574CDT 1574CDM
18 TXINHA 17 RXA 16 RXA 15 TXB 14 TXB 13 TXINHB 12 RXB 11 RXB
HI-1573, HI-1574
PIN DESCRIPTIONS
PIN (DIP & SOIC)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SYMBOL
VDDA BUSA BUSA RXENA GNDA VDDB BUSB BUSB RXENB GNDB RXB RXB TXINHB TXB TXB RXA RXA TXINHA TXA TXA
FUNCTION
power supply analog output analog output digital input power supply power supply analog output analog output digital input power supply digital output digital output digital input digital input digital input digital output digital output digital input digital input digital input
DESCRIPTION
+3.3 volt power for channel A MIL-STD-1533 bus driver A, positive signal MIL-STD-1553 bus driver A, negative signal Receiver A enable. If low, forces RXA and RXA low (HI-1573) or High (HI-1574) Ground for channel A +3.3 volt power for channel B MIL-STD-1533 bus driver B, positive signal MIL-STD-1553 bus driver B, negative signal Receiver B enable. If low, forces RXB and RXB low (HI-1573) or High (HI-1574) Ground for channel B Receiver B output, inverted Receiver B output, non-inverted Transmit inhibit, channel B. If high BUSB, BUSB disabled Transmitter B digital data input, non-inverted Transmitter B digital data input, inverted Receiver A output, inverted Receiver A output, non-inverted Transmit inhibit, channel A. If high BUSA, BUSA disabled Transmitter A digital data input, non-inverted Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1573 family of data bus transceivers contains differential voltage source drivers and differential receivers. They are intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. TRANSMITTER Data input to the device's transmitter section is from the complementary CMOS inputs TXA/B and TXA/B. The transmitter accepts Manchester II bi-phase data and converts it to differential voltages on BUSA/B and BUSA/B. The transceiver outputs are either direct or transformer coupled to the MIL-STD-1553 data bus. Both coupling methods produce a nominal voltage on the bus of 7.5 volts peak to peak. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are either at a logic "1" or logic "0" simultaneously. A logic "1" applied to the TXINHA/B input will force the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B. RECEIVER The receiver accepts bi-phase differential data from the MIL-STD-1553 bus through the same direct or transformer coupled interface as the transmitter. The receiver's differential input stage drives a filter and threshold comparator that produces CMOS data at the RXA/B and RXA/B output pins. Each set of receiver outputs can be independently forced to a logic "0" (HI-1573) or logic "1" (HI-1574) by setting RXENA or RXENB low. MIL-STD-1553 BUS INTERFACE A direct coupled interface (see Figure 2) uses a 1:2.5 ratio isolation transformer and two 55 ohm isolation resistors between the transformer and the bus. In a transformer coupled interface (see Figure 3), the transceiver is connected to a 1:1.79 isolation transformer which in turn is connected to a 1:1.4 coupling transformer. The transformer coupled method also requires two coupling resistors equal to 75% of the bus characteristic impedence (Zo) between the coupling transformer and the bus.
HOLT INTEGRATED CIRCUITS 2
HI-1573, HI-1574
Each Channel
TRANSMITTER
Data Bus Isolation Transformer Coupler Network Direct or Transformer
BUSA/B
TXA/B Transmit Logic TXA/B TXINHA/B RECEIVER RXA/B Receive Logic RXA/B RXENA/B
BUSA/B Slope Control
Input Filter
Comparator
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
Vin (Line to Line)
RXA/B RXA/B
HOLT INTEGRATED CIRCUITS 3
HI-1573, HI-1574 ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD) Logic input voltage range Receiver differential voltage Driver peak output current Power dissipation at 25C ceramic DIL, derate Solder Temperature Junction Temperature Storage Temperature -0.3 V to +5 V -0.3 V dc to +3.6 V 10 Vp-p Temperature Range +1.0 A 1.0 W 7mW/C 275C for 10 sec. 175C -65C to +150C Industrial Screening.........-40C to +85C Hi-Temp Screening........-55C to +125C Military Screening..........-55C to +125C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage VDD....................................... 3.3V... 5%
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage Total Supply Current
SYMBOL
VDD ICC1 ICC2 ICC3
CONDITION
Not Transmitting Transmit one channel @ 50% duty cycle Transmit one channel @ 100% duty cycle Not Transmitting Transmit one channel @ 100% duty cycle Digital inputs Digital inputs Digital inputs Digital inputs IOUT = -1.0mA, Digital outputs IOUT = 1.0mA, Digital outputs
MIN
3.15
TYP
3.30 4 225 425
MAX
3.45 10 250 500 0.06
UNITS
V mA mA mA W W VDD
Power Dissipation
PD1 PD2
0.3 70%
0.5
Min. Input Voltage Max. Input Voltage Min. Input Current Max. Input Current Min. Output Voltage Max. Output Voltage RECEIVER Input resistance Input capacitance
(HI) (LO) (HI) (LO) (HI) (LO)
VIH VIL IIH IIL VOH VIH
30% 20 -20 90% 10%
VDD A A VDD VDD
(Measured at Point "AD" in Figure 2 unless otherwise specified) RIN CIN CMRR VIN VICM Detect No Detect VTHD VTHND VTHD VTHND 1 Mhz Sine Wave (Measured at Point "AD" in Figure 2) 1 MHz Sine Wave (Measured at Point "AT" in Figure 3) Differential -5.0 1.15 Differential Differential 40 9 5.0 20.0 0.28 0.86 14.0 0.20 20 5 Kohm pF dB Vp-p V-pk Vp-p Vp-p Vp-p Vp-p
Common mode rejection ratio Input Level Input common mode voltage Threshold Voltage - Direct-coupled
Theshold Voltage - Transformer-coupled =
Detect
No Detect
HOLT INTEGRATED CIRCUITS 4
HI-1573, HI-1574
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
TRANSMITTER Output Voltage
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
(Measured at Point "AD" in Figure 2 unless otherwise specified) Direct coupled Transformer coupled VOUT VOUT VON Direct coupled VDYN VDYN ROUT COUT 35 ohm load (Measured at Point "AD" in Figure 2) 70 ohm load (Measured at Point "AT" in Figure 3) Differential, inhibited 35 ohm load (Measured at Point "AD" in Figure 2) 70 ohm load (Measured at Point "AT" in Figure 3) Differential, not transmitting 1 MHz sine wave -90 -250 10 15 6.0 18.0 9.0 27.0 10.0 90 250 Vp-p Vp-p mVp-p mV mV Kohm pF
Output Noise Output Dynamic Offset Voltage
Transformer coupled Output resistance Output Capacitance
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
RECEIVER Receiver Delay Receiver Enable Delay TRANSMITTER Driver Delay Rise time Fall Time Inhibit Delay
SYMBOL
tDR tREN
TEST CONDITIONS
From input zero crossing to RXA/B or RXA/B From RXENA/B rising or falling edge to RXA/B or RXA/B
MIN
TYP
MAX
450 40
UNITS
ns ns
(Measured at Point "AD" in Figure 2)
(Measured at Point "AD" in Figure 2) tDT tr tf tDI-H tDI-L TXA/B, TXA/B to BUSA/B, BUSA/B 35 ohm load 35 ohm load Inhibited output Active output 100 100 150 300 300 100 150 ns ns ns ns ns
TRANSMITTER TXA/B TXA/B TXINHA/B BUSA/B
1:2.5
55 W 35 W Point "AD"
BUSA/B
Isolation Transformer
55 W
55 W Point "AD" 35 W 55 W
2.5:1
RECEIVER RXA/B RXA/B
Isolation Transformer RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS 5
HI-1573, HI-1574
TRANSMITTER TXA/B TXA/B TXINHA/B 52.5 W (.75 Zo) 35 W (.5 Zo) 52.5 W (.75 Zo) BUSA/B
1:1.79
Point "AT"
1:1.4
52.5 W (.75 Zo) 35 W (.5 Zo)
BUSA/B
Isolation Transformer Point "AT" 1.79:1
Coupling Transformer
52.5 W (.75 Zo)
1.4:1
RECEIVER RXA/B RXA/B
Coupling Transformer
Isolation Transformer RXENA/B
Figure 3. Transformer Coupled Test Circuits
HEAT SINK - ESOIC & CHIP-SCALE PACKAGE
Both the HI-1573PSI/T/M and HI-1574PSI/T/M use a 20pin thermally enhanced SOIC package. The HI1573PCI/T and HI-1574PCI/T use a plastic chip-scale package. These packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated and may be soldered to any convenient power or ground plane..
APPLICATIONS NOTE
Holt Applications Note AN-500 provides circuit design notes regarding the use of Holt's family of MIL-STD-1553 transceivers. Layout considerations, as well as recommended interface and protection components are included.
THERMAL CHARACTERISTICS
PART NUMBER HI-1573PSI / T / M HI-1574PSI / T / M HI-1573CDI / T / M HI-1574CDI / T / M HI-1573PCI / T HI-1574PCI / T PACKAGE STYLE CONDITION Heat sink unsoldered Heat sink soldered Socketed Heat sink unsoldered OJA 54C/W 47C/W 62C/W 49C/W JUNCTION TEMPERATURE TA=25C 52C 49C 56C 50C TA=85C TA=125C 112C 109C 116C 110C 152C 149C 156C 150C
20-pin Thermally enhanced plastic SOIC (ESOIC) 20-pin Ceramic side-brazed DIP 44-pin Plastic chipscale package
Data taken at VDD=3.3V, continuous transmission at 1Mbit/s, single transmitter enabled.
HOLT INTEGRATED CIRCUITS 6
HI-1573, HI-1574
ORDERING INFORMATION
PART NUMBER
HI-1573PSI HI-1573PST HI-1573PSM HI-1573CDI HI-1573CDT HI-1573CDM HI-1573PCI HI-1573PCT HI-1574PSI HI-1574PST HI-1574PSM HI-1574CDI HI-1574CDT HI-1574CDM HI-1574PCI HI-1574PCT
IDLE STATE
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
PACKAGE DESCRIPTION
20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 44 PIN CHIP SCALE PACKAGE 44 PIN CHIP SCALE PACKAGE 20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 44 PIN CHIP SCALE PACKAGE 44 PIN CHIP SCALE PACKAGE
TEMPERATURE RANGE
-40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C
PROCESS FLOW
I T M I T M I T I T M I T M I T
BURN IN
NO NO YES NO NO YES NO NO NO NO YES NO NO YES NO NO
LEAD FINISH
SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER SOLDER SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER SOLDER
Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink) WB - Wide Body
HOLT INTEGRATED CIRCUITS 7
PACKAGE DIMENSIONS
inches (millimeters)
20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced)
.0105 .0015 (.2667 .0381)
Heat sink stud on bottom of package.
Package Type: 24HEW
.5035 .0075 (12.789 .191)
.300 TYP. (7.620)
.025 Min.. (.635)
.4065 .0125 (10.325 .318)
Top View
.296 .003 (7.518 .076)
.215 TYP. (5.461)
Bottom View
.018 TYP. (.457)
SEE DETAIL A
.025 Min.. (.635) .090 .010 (2.286 .254)
0 to 8 .050 TYP (1.27) .033 .017 (.838 .432) DETAIL A
.0075 .0035 (.191 .889)
20-PIN CERAMIC SIDE-BRAZED DIP
PACKAGE TYPE: 20C
1.000 .010 (25.400 .254) .310 010 . (7.874 .254) .050 TYP. (1.270 TYP.) .200 MAX. (5.080 MAX.) .085 .009 (2.159 .229)
.300 010 . (7.620 .254)
.125 MIN. (3.175 MIN.)
.017 .002 (.432 .051)
.100 .005 (2.540 .127)
.010 + 002/-.001 . (.254 .051/.025)
HOLT INTEGRATED CIRCUITS 8
PACKAGE DIMENSIONS
millimeters
44-PIN PLASTIC CHIP-SCALE PACKAGE
Heat sink stud on bottom of package.
7.00 .10
5.65 .15
0.50 7.00 .10 5.65 .15 0.25 typ
0.40 .05 0.90 .10 0.2 typ
HOLT INTEGRATED CIRCUITS 9

▲Up To Search▲

Price & Availability of HI-1573

	To Download HI-1573 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .